A low power 12-bit and 25-MS/s pipelined ADC for the ILC / ECAL integrated readout

The design of a fully integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here two prototypes of a 12-bit 25-MS/s analog to digital converter using a pipelined architecture. The first one is composed of ten 1.5 bit stages and a 2 bit full flash ADC which produces the least significant bits (LSB) of the converter. The second prototype is composed of a multi-bit first stage of 2.5 bits, followed by seven 1.5 bit stages as a back-end converter and a 3 bit full flash. A CMOS 0.35 μm process is used, and the dynamic range covered is 2V. The analog part of the converter can be quickly (a couple of μs) switched to a standby mode that reduces the DC power dissipation by a ratio of 1/1000. The total power dissipation of the first prototype is 37mW. For the second chip, the size of the converter’s layout including the digital correction stage is only 1.9mm*0.9mm, and the total power dissipation is 42mW.