Design and performance of the 6 GHz waveform digitizing chip DRS4

The high demands of modern experiments in fast waveform digitizing led to the development of the DRS4 chip, which is a radiation hard switched capacitor array (SCA) fabricated in a 0.25 μm CMOS process. It is capable to digitize 8+1 input channels at sampling rates up to 6 Giga-samples per second (GSPS) with an individual channel depth of 1024 bins and a effective range of 11.5 bits. A novel cascading scheme allows the combination of several channels or even chips to deliver very deep sampling depths or interleaved sampling with up to 48 GSPS. An on-chip PLL ensures high timing accuracy over a wide temperature range. The high analog bandwidth of 850 MHz, low power consumption of 40 mW/channel and fast readout time make this chip attractive for many experiments, replacing traditional ADCs and TDCs.