15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique

Phase-locked loops (PLLs) are widely used for clock generation in modern digital systems. All-digital PLLs have been proposed to address design issues in conventional analog PLLs. However, current all-digital PLLs require custom circuit design, and therefore cannot fully leverage advanced automated digital design flows. While fully synthesizable PLLs have been reported, they suffer from high power consumption and large area. This arises because each stage of the ring needs to have a large number of parallel tristate buffers/inverters in order to achieve the necessary frequency resolution. Moreover, custom-designed cells are required in prior synthesizable PLLs, introducing additional place-and-route (P&R) steps, leading to poor portability, integration, and scalability. To address these issues, this paper proposes a fully synthesizable PLL based solely on a standard digital library, with a current-output digital-to-analog converter (DAC) for maintaining frequency linearity and duty balance, an interpolative phase-coupled oscillator for minimizing the output phase imbalance from automatic P&R, as well as an edge injection technique for avoiding injection-pulse width issues.