• DocumentCode
    2623179
  • Title

    The WASP demonstrator programme: the engineering of a wafer-scale system

  • Author

    Jalowiecki, I.P. ; Hedge, S.J.

  • Author_Institution
    Aspex Microsyst. Ltd., Brunel Univ., Uxbridge, UK
  • fYear
    1990
  • fDate
    23-25 Jan 1990
  • Firstpage
    43
  • Lastpage
    49
  • Abstract
    The aim of the Brunel University/Aspex Microsystems WASP (WSI Associative String Processor) project is the production of high performance, cost-effective, practical monolithic Wafer-Scale Parallel Processing systems. The Associative String Processor (ASP) architecture is a massively parallel, fine-grain architecture, suitable for VLSI, ULSI and WSI fabrication. Following a considerable period of test chip experimentation, addressing fundamental WSI design issues, this work graduated to a programme of first technology, and then functional demonstrators. Designed to progress towards a practical WASP in a series of carefully planned steps, these devices prove the feasibility of the WASP architecture and provide engineering data and proof of principle unobtainable by any other means. The authors summarise the demonstrator programme to date, including the test results from the first technology demonstrator (WASP 1) and the architecture of the second technology demonstrator (WASP 2)
  • Keywords
    VLSI; cellular arrays; integrated circuit technology; microprocessor chips; parallel architectures; Aspex Microsystems; Associative String Processor; Brunel University; WASP demonstrator programme; WSI Associative String Processor; Wafer-Scale Parallel Processing systems; demonstrator programme; engineering data; fine-grain architecture; proof of principle; test chip experimentation; test results; wafer-scale system; Application specific processors; Communication system control; Contracts; Decoding; Design engineering; Parallel processing; Production systems; Testing; Ultra large scale integration; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-8186-9013-5
  • Type

    conf

  • DOI
    10.1109/ICWSI.1990.63881
  • Filename
    63881