Resource-Efficient Programmable Trigger Units for Post-Silicon Validation

Author

Ko, Ho Fai ; Nicolici, Nicola

Author_Institution

Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, ON, Canada

fYear

2009

fDate

25-29 May 2009

Firstpage

17

Lastpage

22

Abstract

The decisions on when to acquire debug data during post-silicon validation are determined by trigger events that are programmed into on-chip trigger units. In this paper, we investigate how to design trigger units that are both resource-efficient and runtime programmable. To achieve these two goals, we introduce new architectural features, as well as an algorithm for automatically mapping trigger events onto trigger units.

Keywords

computer debugging; elemental semiconductors; logic design; logic testing; programmable circuits; silicon; system-on-chip; trigger circuits; automatically mapping trigger event algorithm; debug data testing; on-chip trigger unit; post-silicon validation debug data testing; resource-efficient programmable trigger; runtime programmable architectural feature; Automatic control; Circuits; Data acquisition; Detectors; Event detection; Logic; Runtime; Signal analysis; Signal design; Testing; false trigger analysis; post-silicon validation; programmable trigger unit;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2009 14th IEEE European

Conference_Location

Seville

Print_ISBN

978-0-7695-3703-0

Type

conf

DOI

10.1109/ETS.2009.35

Filename

5170454