Modeling of power supply parasitics for selecting on-wafer bypass capacitance in high-speed IC designs

Author

He, Qiurong ; Feng, Milton

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

2004

fDate

8-10 Sept. 2004

Firstpage

175

Lastpage

178

Abstract

We have developed a model for power supply parasitics to select properly the on-wafer bypass capacitor values in high-speed IC designs. The model can allows the chip area to be minimized while maintaining circuit performance. The procedures to develop this model are described and are suitable for all device technologies. An InGaP/GaAs HBT transimpedance amplifier with 10-GHz bandwidth was designed and fabricated. The simulation with the model matches the measured results very well.

Keywords

amplifiers; bipolar integrated circuits; capacitors; gallium arsenide; gallium compounds; heterojunction bipolar transistors; high-speed integrated circuits; indium compounds; integrated circuit design; integrated circuit modelling; minimisation; 10 GHz; HBT transimpedance amplifier; InGaP-GaAs; gallium arsenide; high-speed IC designs; indium gallium phosphide; on-wafer bypass capacitance; power supply parasitics modeling; Bandwidth; Capacitors; Circuit optimization; Circuit simulation; Gallium arsenide; Heterojunction bipolar transistors; High speed integrated circuits; Integrated circuit modeling; Parasitic capacitance; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 2004. Digest of Papers. 2004 Topical Meeting on

Print_ISBN

0-7803-8703-1

Type

conf

DOI

10.1109/SMIC.2004.1398196

Filename

1398196