A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits

A novel method to detect a defective I_DDQ on top of high background current is proposed. Instead of the conventional approach that measures the quiescent current drawn by the circuit-under-test (CUT), the proposed method is based on the measurement of the voltage drop in a resistor spatially laid-out along the CUT. Resistive shorts with a defective current of 2.14 muA on top of 83.11 muA of leakage current have been detected in a 65 nm CMOS test chip with controllable leakage. The proposed method also provides facilities to locate the defect in addition to detect it.