Delay modeling for power noise-aware design in Spartan-3A FPGAs

There is a continuously increasing demand for lower power consumption and higher operating frequencies in digital systems. In addition, external or operation-induced disturbances may significantly affect circuit functionality or performance. This paper analyzes the effect of power supply disturbances on the propagation delays of digital circuits implemented in Spartan-3A FPGAs and demonstrates that a previously proposed time management methodology can successfully be applied to the design of circuits with increased robustness to these disturbances. Experimental results are presented that support the claimed contributions of the work.