A CMOS power-delay model for CAD optimization tools

Author

Delaurenti, M. ; Masera, G. ; Piccinini, G. ; Roch, M. Ruo ; Zamboni, M.

Author_Institution

Dipt. di Elettronica, Politecnico di Torino, Italy

fYear

1999

fDate

4-5 Mar 1999

Firstpage

72

Lastpage

77

Abstract

The need of fast and reliable models for CMOS gates has grown in importance not only for the simulation of digital VLSI circuits, but also for their optimization. In a library based design the optimum of speed is a basic step to achieve high performance, but also power consumption must be considered with increasing care. A simultaneous power-delay evaluation can be performed using a new model developed for sub-micron CMOS technologies, allowing better multi-objective optimization

Keywords

CMOS digital integrated circuits; VLSI; circuit CAD; circuit optimisation; delays; integrated circuit modelling; software libraries; CAD optimization tools; CMOS power-delay model; circuit optimization; digital VLSI circuits; library based design; multi-objective optimization; power consumption; simultaneous power-delay evaluation; sub-micron CMOS technologies; CMOS digital integrated circuits; CMOS technology; Circuit simulation; Delay estimation; Design optimization; Energy consumption; MOS devices; Semiconductor device modeling; Software libraries; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low-Power Design, 1999. Proceedings. IEEE Alessandro Volta Memorial Workshop on

Conference_Location

Como

Print_ISBN

0-7695-0019-6

Type

conf

DOI

10.1109/LPD.1999.750405

Filename

750405