21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS

Author

Szortyka, V. ; Qixian Shi ; Raczkowski, Kuba ; Parvais, B. ; Kuijk, Maarten ; Wambacq, Piet

Author_Institution

imec, Heverlee, Belgium

fYear

2014

fDate

9-13 Feb. 2014

Firstpage

366

Lastpage

367

Abstract

For high data-rate communication at 60GHz using the IEEE 802.11ad standard, the LO synthesis needs both a low-noise VCO and low in-band phase noise. In the PLL shown in this paper, a QVCO with superharmonic passive coupling exhibits a large swing and low phase noise even with a 0.9V supply. In-band phase noise is reduced thanks to the use of a sub-sampling phase detector (SSPD), earlier introduced for low-GHz PLLs [1]. As most of the divider chain and the charge pump (CP) can be powered down in the sub-sampling mode, power consumption is also reduced.

Keywords

CMOS integrated circuits; charge pump circuits; field effect MIMIC; jitter; millimetre wave oscillators; phase detectors; phase locked loops; phase noise; telecommunication standards; voltage-controlled oscillators; wireless LAN; CMOS technology; IEEE 802.11ad standard; LO synthesis; PLL; QVCO; SSPD; charge pump; divider chain; frequency 60 GHz; in-band phase noise; low-noise VCO; phase locked loops; power 42 mW; size 40 nm; subsampling phase detector; superharmonic passive coupling; voltage 0.9 V; CMOS integrated circuits; Couplings; Frequency synthesizers; Phase frequency detector; Phase locked loops; Phase noise; Power harmonic filters;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4799-0918-6

Type

conf

DOI

10.1109/ISSCC.2014.6757472

Filename

6757472