Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

Author

Kavalieros, Jack ; Doyle, Brian ; Datta, Suman ; Dewey, Gilbert ; Doczy, Mark ; Jin, Boyuan ; Lionberger, Dan ; Metz, Matthew ; Rachmady, Willy ; Radosavljevic, Marko ; Shah, Uday ; Zelick, Nancy ; Chau, Robert

Author_Institution

Intel Corp., Hillsboro, OR

fYear

0

fDate

0-0 0

Firstpage

50

Lastpage

51

Abstract

We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS trigate transistors are demonstrated with I_DSAT=1.4 mA/mum and 1.1 mA/mum respectively (I_OFF=100nA/mum, V_CC=1.1V and L_G=40nm) with excellent short channel effects (SCE)-DIBL and subthreshold swing, DeltaS. The contributions of strain, the lang100rang vs. lang110rang substrate orientations, high-k gate dielectrics, and low channel doping are investigated for a variety of channel dimensions and FIN profiles. We observe no evidence of early parasitic corner transistor turn-on in the current devices which can potentially degrade I_ON-I_OFF and DeltaS

Keywords

MOSFET; dielectric materials; high-k dielectric thin films; metallic thin films; FIN profiles; NMOS transistors; PMOS transistors; channel doping; high-k gate dielectrics; metal gate electrodes; strain engineering; substrate orientations; tri-gate transistor architecture; Capacitive sensors; Degradation; Dielectric substrates; Electrodes; Etching; Lifting equipment; MOS devices; Manufacturing; Postal services; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705211

Filename

1705211