Power optimization of LUT based FPGA circuits

In this paper, a new method for decreasing the power consumption in LUT based FPGA circuits is presented that attempts to reduce the switching activity among LUT blocks. To achieve this, we have introduced the fake register insertion method and combined it with retiming method. Fake registers have been inserted on low-transition wires around high-transition wires to force the synthesis tool to direct those low-transition wires on LUTs´ outputs. In other words, high-transition wires will be likely placed inside LUT blocks and consequently, the off-block switching activity among LUT blocks gets reduced. Retiming is used to move registers that have been located on high-transition wires in order to prevent the synthesis tool to place them on LUTs´ outputs. As of benchmarking, two of ISCAS89 benchmark library circuits were employed. Experimental results have shown that this scheme will decrease the off-block switching of the implemented circuits up to 25%.