Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window

Author

Ahn, Young Joon ; Choe, Jeong-Dong ; Lee, Jong Jin ; Choi, Donguk ; Cho, Eun Suk ; Choi, Byung Yong ; Lee, Se-Hoon ; Sung, Suk-Kang ; Lee, Choong-Ho ; Cheong, Seong Hwee ; Lee, Dong Kak ; Kim, Seung Beom ; Park, Donggun ; Ryu, Byung-Il

Author_Institution

Device Res. Team, Samsung Electron. Co., Gyeonggi

fYear

0

fDate

0-0 0

Firstpage

88

Lastpage

89

Abstract

This paper presents the trap layer engineered body-tied FinFET device for MLC NAND flash application. The device design parameters for high density NAND flash memory have been considered, and the advantages of FinFET structure and high-k blocking dielectric in such device have been demonstrated. Based on the WN nano-dot memory device, the trap layer engineering using nitride layer has been performed, and the results show that the memory window is improved from 2.6 V to 7.8 V by utilizing engineered trap layer at 14 MV/cm F-N programming, and it is proposed as a possible MLC NAND device structure

Keywords

MOSFET; NAND circuits; dielectric materials; flash memories; 2.6 to 7.8 V; MLC; NAND flash memory; engineered body-tied FinFET device; high-k blocking dielectric; memory window; nanodot memory device; nitride layer; trap layer; Dielectric devices; Electron traps; FinFETs; High K dielectric materials; High-K gate dielectrics; Manufacturing processes; Nanoscale devices; Pulp manufacturing; Research and development; Semiconductor device manufacture;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705230

Filename

1705230