DocumentCode
2626914
Title
A Digital PLL with a Stochastic Time-to-Digital Converter
Author
Kratyuk, Volodymyr ; Hanumolu, Pavan Kumar ; Ok, Kerem ; Mayaram, Kartikeya ; Moon, Un-Ku
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR
fYear
0
fDate
0-0 0
Firstpage
31
Lastpage
32
Abstract
A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test chip has been fabricated in a 0.13mum CMOS process. The DPLL features a 0.7-1.7 GHz oscillator tuning range, 6.9ps rms jitter and consumes 17mW while operating at 1.2GHz
Keywords
CMOS integrated circuits; digital phase locked loops; digital-analogue conversion; timing jitter; 0.13 micron; 0.7 to 1.7 GHz; 17 mW; CMOS technology; delta-sigma dithering; digital phase locked loops; stochastic time-to-digital converter; Bandwidth; Clocks; Digital filters; Jitter; Phase detection; Phase frequency detector; Phase locked loops; Signal resolution; Stochastic processes; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
1-4244-0006-6
Type
conf
DOI
10.1109/VLSIC.2006.1705297
Filename
1705297
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