DocumentCode
2626963
Title
A Multiphase Delay-Locked Loop for 0.125-2Gbps 0.18/spl mu/m CMOS Transmitter
Author
Moon, Yongsam ; Shim, Daeyun
Author_Institution
Silicon Image Inc., Sunnyvale, CA
fYear
0
fDate
0-0 0
Firstpage
35
Lastpage
36
Abstract
A 0.18-mum CMOS DLL generates equally-spaced multiphase clocks over 16times range from 31.25 to 500MHz using a duty-cycle corrector and a lock detector with 32times lock range, which is at least 3.5times wider comparing with conventional multiphase DLL´s. Measured TX data eyes have <4% eye unevenness, which is equivalent to <1% clock unevenness, over the data rates of 0.125 to 2Gbps
Keywords
CMOS integrated circuits; clocks; delay lock loops; digital phase locked loops; transmitters; 0.125 to 2 Gbit/s; 0.18 micron; 31.25 to 500 MHz; CMOS transmitter; DLL; duty-cycle corrector; equally-spaced multiphase clocks; lock detector; multiphase delay-locked loop; Clocks; Delay effects; Detectors; Frequency; Moon; Phase detection; Phase locked loops; Silicon; Transmitters; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
1-4244-0006-6
Type
conf
DOI
10.1109/VLSIC.2006.1705299
Filename
1705299
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