DocumentCode
2627636
Title
Reduced-latency stochastic decoding of LDPC codes over GF(q)
Author
Sarkis, Gabi ; Gross, Warren J.
Author_Institution
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, QC, Canada
fYear
2010
fDate
12-15 April 2010
Firstpage
994
Lastpage
998
Abstract
Non-binary LDPC codes have excellent error-correcting performance but have not yet been widely adopted due to the high decoder implementation complexity. Stochastic decoding has been proposed as a low-complexity decoding algorithm for non-binary LDPC codes. In this paper we present a new stochastic decoding algorithm for non-binary LDPC codes using tracking forecast memories that has higher throughput and lower latency than previous stochastic decoders.
Keywords
computational complexity; decoding; error correction; parity check codes; error-correcting performance; high decoder implementation complexity; low-complexity decoding; nonbinary LDPC codes; reduced-latency stochastic decoding; Code standards; Computer errors; Delay; Digital video broadcasting; Iterative decoding; Parity check codes; Polynomials; Stochastic processes; Throughput; WiMAX;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless Conference (EW), 2010 European
Conference_Location
Lucca
Print_ISBN
978-1-4244-5999-5
Type
conf
DOI
10.1109/EW.2010.5483537
Filename
5483537
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