Using the combinatorial optimization approach for DVS in high performance processors

Currently, in high performance computer systems, processors are faster and have vastly increased in performance and computational power. It is important for system designers to get an early estimation of power dissipation to meet the challenging methodologies for power dissipation reduction and optimization. In addition to the current design methodologies, the designer might need to consider the factors that affect the power and the interaction of these factors in practice. This paper presents a design technique for dynamic voltage scaling (DVS) for microprocessor´s power dissipation control using the combinatorial design approach. The DVS unit dynamically alter processor´s throughput for energy-efficiency by scaling down the supply voltage as well as clock frequency such that the actual delay of the chip meets the target performance. Whilst the combinatorial design is used to get an optimal interaction of the factors that affect the power to get optimal power dissipation estimation for the designer. Simulation and results are used to verify the theoretical background and optimization of the design approach which shows satisfactory results.