A versatile digital readout system for the PANDA MVD

The Micro Vertex Detector (MVD) for the PANDA experiment at the future Facility for Antiproton and Ion Research (FAIR) will be the innermost high precision vertexing detector, necessary for e.g. identification of displaced vertices of D-meson decays. Challenges include its triggerless readout and a high occupancy due to its proximity to the interaction point. Thus, the MVD design foresees hybrid silicon pixel sensors for the inner layers, silicon strip sensors for the outer layers and a custom frontend chip which can sustain high data rates for the readout. During the development of the MVD, a flexible system is needed to test pixel and strip detector prototypes. Both the suitability of existing concepts and newly developed circuits have to be evaluated. In the following, a versatile digital readout system for device testing and evaluation on a tabletop scale is presented along with application examples from practical use. Its FPGA-based hardware, modular firmware and software are the key features which provide great flexibility and ease of use at the same time.