DocumentCode
2628497
Title
A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time
Author
Luk, Wing K. ; Cai, Jin ; Dennard, Robert H. ; Immediato, Michael J. ; Kosonocky, Stephen V.
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY
fYear
0
fDate
0-0 0
Firstpage
184
Lastpage
185
Abstract
3T1D is a non-destructive read DRAM cell with three transistors (T) and a gated diode (D). The gated diode acts as a storage device and an amplifier, leading to low voltage, high speed and high tolerance to variability, and comparing favorably to conventional 3T gain cell and 6T SRAM cell. Hardware measurements in 90 nm SOI showed the 3T1D achieved longer retention than the 3T. Retention, speed and scaling perspectives for future technology are presented
Keywords
DRAM chips; integrated circuit design; low-power electronics; silicon-on-insulator; 90 nm; DRAM; SOI; amplifier device; gated diode; nondestructive read cell; storage device; Boosting; Capacitance; Diodes; Hardware; Joining processes; Low voltage; MOS capacitors; Random access memory; Velocity measurement; Virtual colonoscopy;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
1-4244-0006-6
Type
conf
DOI
10.1109/VLSIC.2006.1705371
Filename
1705371
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