Low Power SOC Design Using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for Sub-100-nm LSTP Technology

Author

Ozawa, Osamu ; Fukuoka, Kazuki ; Igarashi, Yasuto ; Kuraishi, Takashi ; Yasu, Yosihiko ; Maki, Yukio ; Ipposhi, Takashi ; Ochiai, Toshihiko ; Shirahata, Masayoshi ; Ishibashi, Koichiro

Author_Institution

Renesas Technol. Corp., Tokyo

fYear

0

fDate

0-0 0

Firstpage

186

Lastpage

187

Abstract

The bodies of partially depleted SOI devices are selectively biased so that circuits operate at low supply voltages without area overhead. Applying forward body bias to logic gates reduces delay variation by 7-21%. A level shifter (LF) and data retention FF (DRFF) circuits can operate at lower supply voltages below 1.0-V when the body bias of the key transistors is suitably controlled. The technology reduces operating and standby power of SOC with 90-nm LSTP CMOS technology by 40 and 98%, respectively

Keywords

CMOS logic circuits; isolation technology; logic design; low-power electronics; nanotechnology; silicon-on-insulator; system-on-chip; 90 nm; LSTP CMOS technology; SOC; data retention; forward body bias; level shifter; low power design; partial trench isolation; partially depleted SOI devices; CMOS logic circuits; CMOS technology; Delay; Inverters; Isolation technology; Logic circuits; Logic devices; Logic gates; Low voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0006-6

Type

conf

DOI

10.1109/VLSIC.2006.1705372

Filename

1705372