Design of A Low-Power-Consumption and High-Performance Sigma-Delta Modulator

Author

Yueyang, Chen ; Shun, Zhong ; Hua, Dang

Author_Institution

Sch. of Inf. & Electron, Beijing Inst. of Technol., Beijing, China

Volume

3

fYear

2009

fDate

March 31 2009-April 2 2009

Firstpage

375

Lastpage

379

Abstract

Based on the switched-capacitor discrete time sampling technique in 0.18 um CMOS technology, a modified single loop 3rd order sigma-delta modulator used for a resolution of 16 bit sigma-delta ADC was proposed. The analysis of sigma-delta modulator structures and the design flow were given. The method to design NTF and the principle to determine the index of circuit module were also introduced. The modulator is proved to be robustness, the high performance in stability, anti- mismatch, chip area, and the power consumption is only 2.6 mw when the power supply is 2.8 V.

Keywords

CMOS integrated circuits; sigma-delta modulation; CMOS technology; circuit module; complementary metal-oxide-semiconductor integrated circuits; high performance sigma-delta modulator; low power consumption sigma-delta modulator; sigma-delta ADC; stability; switched capacitor discrete time sampling; Analog circuits; CMOS technology; Circuit noise; Circuit stability; Delta-sigma modulation; Dynamic range; Noise shaping; Power dissipation; Robust stability; Signal to noise ratio; index of circuit module; sigma-delta modulators; structure of modul- ators;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Information Engineering, 2009 WRI World Congress on

Conference_Location

Los Angeles, CA

Print_ISBN

978-0-7695-3507-4

Type

conf

DOI

10.1109/CSIE.2009.772

Filename

5170866