System-level modeling of microprocessor reliability degradation due to TDDB

Author

Chang-Chih Chen ; Soonyoung Cha ; Milor, Linda

Author_Institution

Sch. of Electr. & Comptuer Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2014

fDate

26-28 Nov. 2014

Firstpage

1

Lastpage

6

Abstract

Time-dependent dielectric breakdown (TDDB) is leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of TDDB on state-of-art microprocessors and to estimate microprocessor lifetimes due to TDDB. Our methodology finds the detailed electrical stress and temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we do timing analysis on the critical paths of a microprocessor using our methodology to characterize microprocessor performance degradation due to TDDB. In addition, we study DC noise margins in conventional 6T SRAM cells as a function of TDDB degradation to provide insights on reliability of memories embedded within microprocessors under realistic use conditions.

Keywords

SRAM chips; electric breakdown; integrated circuit modelling; integrated circuit reliability; microprocessor chips; timing; DC noise margins; TDDB; conventional 6T SRAM cells; device-level models; electrical stress profiles; memories reliability; microprocessor lifetimes; microprocessor performance degradation; modern microprocessors; standard benchmarks; thermal profiles; time-dependent dielectric breakdown; timing analysis; Degradation; Electric breakdown; Integrated circuit modeling; Logic gates; Microprocessors; Reliability; Stress; SRAM; aging; cache; gate oxide breakdown; microprocessor; modeling; reliability; timing analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Design of Circuits and Integrated Circuits (DCIS), 2014 Conference on

Conference_Location

Madrid

Type

conf

DOI

10.1109/DCIS.2014.7035568

Filename

7035568