Delay and noise formulas for capacitively coupled distributed RC lines

Simple yet useful analytical formulas for delay, slope and crosstalk noise amplitude for capacitively coupled two-, three- and infinite-line systems are derived assuming bus lines and other signal lines in deep-submicron VLSI´s. The calculated results using the derived formulas are extensively compared with SPICE simulation results to demonstrate the validity of the analytical expressions. Two modes have been studied; the case where adjacent lines are driven from the opposite direction and the case where adjacent lines are driven from the same direction. These cases correspond to the typical situations in VLSI designs and include worst cases in terms of noise amplitude and delay. Delay error in approximating the distributed RC lines by N-step π-ladder RC lumped circuit is also investigated