Efficient implementation of pattern matching recognition in heterogeneus architectures

Implementation of pattern recognition algorithms is an important and complex task. These schemes usually perform time and resource consuming operations as 2D FFT. That is the reason why usually they are implemented in heterogeneous platforms with at least one DSP that accelerates the mathematical applications. Nevertheless, even using this specific processor the execution time required can be excessive. Therefore, an efficient use of all the processors available in the platform is mandatory. This paper proposes an efficient implementation of pattern recognition schemes in a heterogeneous platform that includes an ARM processor and a DSP.