DocumentCode
2632137
Title
Designing self-testable cellular arrays
Author
Wu, Cheng-Wen ; Lu, Shyue-Kung
Author_Institution
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
1991
fDate
14-16 Oct 1991
Firstpage
110
Lastpage
113
Abstract
Design-for-testability techniques and built-in self-test structures are presented for cellular arrays based on the M-testability condition, which results in the minimal number of tests. This technique applies to arrays with arbitrary dimensions and various connections. A systolic array multiplier is given as an example, showing an overhead of only 4% for making it M-testable. This method compares favorably with that based on pI-testability. It reduces drastically the testing costs for circuits realized as cellular arrays
Keywords
built-in self test; integrated logic circuits; logic arrays; logic design; multiplying circuits; systolic arrays; ILA; M-testability condition; built-in self-test structures; pI-testability; self-testable cellular arrays; systolic array multiplier; Automatic testing; Built-in self-test; Circuit testing; Costs; Design for testability; Logic arrays; Logic design; Logic testing; Sufficient conditions; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-2270-9
Type
conf
DOI
10.1109/ICCD.1991.139857
Filename
139857
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