Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages

Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current on current signatures and its impact on the diagnosis of such defects. The authors demonstrate that the impact of downstream current is minimized at low power supply (V_dd) values. Therefore, current measurements at low power supply voltages are proposed to enhance bridge diagnosis. Experimental evidence of this behaviour is presented for real devices. Furthermore, current signatures measured at V_VLV are used for the diagnosis of fifteen failing 0.18mum technology devices, which are demonstrated to contain a bridging defect.