An RTL-to-GDS2 design methodology for advanced system LSI

Author

Nishiguchi, Nobuyuki

Author_Institution

Semiconductor Technology Academic Research Center (STARC)

fYear

2011

fDate

25-28 Jan. 2011

Firstpage

770

Lastpage

774

Abstract

STARC is developing an RTL-to-GDS2 design methodology for 32nm (and 28nm) system LSIs called STARCAD-CEL. The design methodology focuses on four key areas: low power design, variation aware design and design for manufacturability as well as design productivity. This paper examines several techniques we used to solve issues the in design of challenging, leading edge devices. It also describes the effectiveness of the STARCAD-CEL design methodology when applied to the four key areas.

Keywords

design for manufacture; integrated circuit design; large scale integration; RTL-to-GDS2 design methodology; STARCAD-CEL; advanced system LSI; design for manufacturability; design productivity; low power design; size 28 nm; size 32 nm; variation aware design;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific

Conference_Location

Yokohama

ISSN

2153-6961

Print_ISBN

978-1-4244-7515-5

Type

conf

DOI

10.1109/ASPDAC.2011.5722292

Filename

5722292

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2634821