Design and chip implementation of a heterogeneous multi-core DSP

Author

Chen, Shuming ; Chen, Xiaowen ; Xu, Yi ; Wan, Jianghua ; Lu, Jianzhuang ; Liu, Xiangyuan ; Chen, Shenggang

Author_Institution

Inst. of Microelectron. & Microprocessor, Nat. Univ. of Defense Technol., Changsha, China

fYear

2011

fDate

25-28 Jan. 2011

Firstpage

91

Lastpage

92

Abstract

This paper presents a novel heterogeneous multi-core Digital Signal Processor, named YHFT-QDSP, hosting one RISC CPU core and four VLIW DSP cores. The CPU core is responsible for task scheduling and management, while the DSP cores take charge of speeding up data processing. The YHFT-QDSP provides three kinds of interconnection communication. One is for inner-chip communication between the CPU core and the four DSP cores, the other two for both inner-chip and inter-chip communication amongst DSP cores. The YHFT-QDSP is implemented under SMIC^® 130nm LVT CMOS technology and can run 350MHz@1.2V with 114.49 mm² die area.

Keywords

CMOS integrated circuits; digital signal processing chips; multiprocessing systems; reduced instruction set computing; CMOS technology; RISC CPU core; VLIW DSP cores; YHFT-QDSP; frequency 350 MHz; heterogeneous multi-core digital signal processor; inner-chip communication; interconnection communication; size 130 nm; task management; task scheduling; voltage 1.2 V; Digital signal processing; Digital signal processors; Multicore processing; Random access memory; Reduced instruction set computing; System-on-a-chip; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific

Conference_Location

Yokohama

ISSN

2153-6961

Print_ISBN

978-1-4244-7515-5

Type

conf

DOI

10.1109/ASPDAC.2011.5722312

Filename

5722312