• DocumentCode
    2635354
  • Title

    TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler

  • Author

    Chen, Shuo-Hung ; Lin, Hsiao-Mei ; Hsieh, Ching-Chou ; Huang, Chih-Tsun ; Liou, Jing-Jia ; Chung, Yeh-Ching

  • Author_Institution
    Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • fYear
    2011
  • fDate
    25-28 Jan. 2011
  • Firstpage
    97
  • Lastpage
    98
  • Abstract
    TurboVG is a hardware accelerator for the OpenVG 1.1 library that operates sixteen times faster than an optimized software implementation. This improved efficiency stems from a well-designed hardware-software interaction capable of handling massive data transfers across hierarchical layers without performance loss. By combining multiple TurboVG cores, the library can support screen resolutions of up to Full-HD 1080p.
  • Keywords
    computer graphic equipment; hardware-software codesign; HW-SW codesigned multicore OpenVG accelerator; OpenVG 1.1 library; embedded power profiler; hardware accelerator; hardware-software interaction; massive data transfers; multiple TurboVG cores; vector graphics applications; Central Processing Unit; Field programmable gate arrays; Graphics; Hardware; Software; Software libraries;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific
  • Conference_Location
    Yokohama
  • ISSN
    2153-6961
  • Print_ISBN
    978-1-4244-7515-5
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2011.5722315
  • Filename
    5722315
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2635354