Efficient FPGA-mapping of 1024 point FFT Pipeline SDF Processor

In this paper the efficient mapping of pipeline single path delay feedback (SDF) fast Fourier transform (FFT) processors to FPGAs is considered. By paying special attention to how the design can efficiently be mapped to the course grained hardware structure of a target field programmable gate array (FPGA) better implementation results can be obtained.This is illustrated by mapping a R22 SDF FFT processor, targeted towards Virtex-4 .The FPGA mapping of these designs have been explored in detail. Algorithmic transformations that provide a better mapping is proposed, resulting in implementation achievements that by far outperform earlier published work.For Virtex-4 the results show a better throughput per slice and lesser latency , still not using more memory or DSP48 resources.