Design of a Highly Dependable Beamforming Chip

As CMOS process technology advances towards 32 nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip is designed using 64 reconfigurable Xentium tile processors. A functional dependability analysis for this application was carried out following the IEC standard 62347. To meet the dependability requirements, a dedicated infrastructural IP (IIP) and supporting software and hardware have been designed and included as part of the dependability infrastructure of the chip. This IIP can periodically verify the correctness of the tile processors and coordinate the run-time mapping reconfiguration software to isolate the faulty tiles at run time and assign spare processors for the open DSP tasks. Dependability graphs show a significant improvement of the application chip incorporating the design-for-dependability hardware and software.