Scaling Issues In An 0.15/spl mu/m CMOS Technology With EKV3.0

Author

Kitonaki, E. ; Bazigos, A. ; Bucher, M. ; Puchner, H. ; Bhardwaj, S. ; Papananos, Y.

Author_Institution

Athens Nat. Tech. Univ.

fYear

2006

fDate

22-24 June 2006

Firstpage

151

Lastpage

158

Abstract

Application of the EKV3.0 model to 0.15mum CMOS technology with single poly, and buried channel PMOS, is presented with emphasis on scaling properties of the technology and the model. The EKV3.0 model is illustrated for its fit to NMOS and PMOS drain current, transconductances and output characteristics in weak, moderate and strong inversion over a large temperature range. Scaling properties of the technology and the model are illustrated with fits versus channel length and width. The model is also compared to measured capacitance-voltage characteristics. Furthermore, some comparisons to a BSIM3v3 model for the same technology are provided

Keywords

CMOS integrated circuits; MOSFET; semiconductor device models; 0.15 micron; BSIM3v3 model; CMOS technology; EKV3.0 model; NMOS drain current; NMOS transconductances; PMOS drain current; PMOS transconductances; buried channel PMOS; capacitance-voltage characteristics; CMOS technology; Capacitance measurement; Capacitance-voltage characteristics; Circuit simulation; MOS devices; MOSFET circuits; Predictive models; Semiconductor device modeling; Temperature distribution; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Conference_Location

Gdynia

Print_ISBN

83-922632-2-7

Type

conf

DOI

10.1109/MIXDES.2006.1706557

Filename

1706557