Challenges of high speed digital control in a SiC JFET matrix converter implementation

This paper investigates some of the challenges encountered during the implementation of a high speed digital control for a Silicon Carbide JFET matrix converter which has been designed to meet a specific power density of 20kW/litre with forced air cooling. After a brief introduction on the main features of the hardware implementation of this unique power converter, an insight into the control strategy and controller platform adopted is given with a particular attention to the performance implications of the gate drive circuitry. Results to show the effect of gate driver and controller induced commutation time limitations on output waveform quality are presented.