Noise Modeling Of Static Cmos Gates For Low-noise Circuit Synthesis

Author

Blakiewicz, G. ; Chrzanowska-Jeske, M.

Author_Institution

Gdansk Univ. of Technol.

fYear

2006

fDate

22-24 June 2006

Firstpage

500

Lastpage

503

Abstract

This paper presents an efficient method for supply-current spectrum estimation for the static CMOS family of digital gates. It extends the previous approach (Blackiewicz, 2006), that considered only the noise due to a gate output switching, by including the noise generated by glitching, and short impulses. Estimation of digital circuit noise is used in early design planning of modern mixed-signal system-on-chips (MS-SoCs), composed of sensitive analogue and usually noisy digital blocks, to reduce substrate coupling-noise in analogue blocks through proper floorplan design (Blackiewicz, 2005)

Keywords

CMOS logic circuits; integrated circuit design; integrated circuit noise; logic design; logic gates; system-on-chip; MS-SoC; digital circuit noise; digital gates; gate output switching; low-noise circuit synthesis; mixed-signal system-on-chips; noise modeling; noisy digital blocks; static CMOS gates; substrate coupling noise; supply-current spectrum estimation; Circuit noise; Circuit synthesis; Digital circuits; Electromagnetic interference; Noise generators; Noise level; Noise reduction; Pulse generation; Semiconductor device modeling; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Conference_Location

Gdynia

Print_ISBN

83-922632-2-7

Type

conf

DOI

10.1109/MIXDES.2006.1706630

Filename

1706630