Systolic VLSI architectures for 1-D discrete wavelet transforms

This paper presents systolic VLSI architectures for the discrete wavelet transform (DWT) and inverse discrete wavelet transform (IDWT) which operate on one-dimensional signals. Previously, a dependence graph (DG) of the DWT has been presented which enables systolic mapping techniques to be used to derive DWT architectures. We use this DG to systematically derive new DWT architectures. In addition, we present a DG for the IDWT and use it to systematically derive new IDWT architectures. The resulting DWT and IDWT architectures are scalable with filter length and number of octaves, modular, have high hardware utilization, and use fixed-coefficient multipliers. These properties make them well-suited for VLSI implementation.