Optimal bipartite multi-processor implementation of recurrent DSP algorithm with fixed communication delay

A novel method is proposed to compute the theoretical minimum initiation interval of a recurrent digital signal processing (DSP) algorithm given a know, fixed inter-processor communication delay. In effect, this proposed algorithm seeks to bipartite a given cyclic graph in such a way that, after the inter-processor communication delay is taken into account, the theoretical minimum initiation interval so computed will be guaranteed to be correct, and minimized. This result made a crucial step toward the real time implementation of recurrent DSP algorithms on multi-modules with known, fixed inter-module communication delay.