MultiStage ASIC implementation of the Mersenne Twister pseudorandom number generator

The development of cluster and parallel computers has increased the popularity of implementing the Monte Carlo (MC) computational method in medical and scientific applications. However, having access to these high-performance systems is not easy and a reasonable size system is not yet able to solve many popular Monte Carlo problems near real-time. The Field Programmable Gate Arrays (FPGAs) have been proved to be useful in speeding up the Monte Carlo algorithm since they are able to execute the problem with a high degree of parallelism. As the FPGA and ASIC are being applied for speeding up Monte Carlo simulations as well as for reducing energy consumption, the generation of pseudorandom number (PRN) by hardware becomes one of major developments. The speed in generating the random numbers and the quality of these numbers are main factors in enhancing the performance and accuracy of the method. In this paper, we present the design and implementation of a multistage pipelining-style Mersenne Twister (MT), one of the most widely used pseudorandom number generation method. By implementing the operations in 4 stages, our design is able to achieve throughput of 178 million, 228 million, and 338 million random numbers per second on 0.25 μm, 0.14 μm, and 90 nm processes, respectively. In theory, the implementation can be scaled up to 208 stages and so the throughput can be up to 18 billion random numbers per second.