A 90nm CMOS 5GHz ring oscillator PLL with delay-discriminator based active phase noise cancellation

Ring-oscillators provide a low-cost digital VCO solution in fully integrated PLLs, but due to their supply noise sensitivity and high noise floor, their applications have been limited. A fully integrated feed-forward, delay-discriminator based adaptive noise-cancellation architecture that improves phase noise characteristic of ring-oscillators outside the PLL bandwidth is presented. Proposed technique can improve the phase noise in an arbitrary offset frequency and bandwidth, and it is insensitive to process and temperature variations. The proposed cancellation loop suppresses the phase noise at 1 MHz offset by 12.5dB and reference spur by 13dB, with 3.7mA power consumption. The measured phase noise at 1 MHz offset is -105 dBc/Hz. The proposed PLL is fabricated in 90 nm CMOS with current consumption of 24.7 mA with the cancellation technique enabled from a voltage supply of 1.2 V.