DocumentCode
2641985
Title
A novel low-power 64-point pipelined FFT/IFFT processor for OFDM applications
Author
Yu, Chu ; Liao, Yi-Ting ; Yen, Mao-Hsu ; Hsiung, Pao-Ann ; Chen, Sao-Jie
Author_Institution
Dept. of Electron. Eng., Nat. ILan Univ., Ilan, Taiwan
fYear
2011
fDate
9-12 Jan. 2011
Firstpage
441
Lastpage
442
Abstract
This paper presents a novel pipelined FFT/IFFT processor for OFDM applications. The proposed architecture employs a low-complexity complex multiplier and a constant complex multiplier to eliminate the need of ROM tables, thus consumes lower power than the existing works. Finally, this design spends about 33.6K gates, and the power consumption is about 9.8mW at 20MHz.
Keywords
OFDM modulation; fast Fourier transforms; OFDM application; ROM tables; constant complex multiplier; frequency 20 MHz; low power 64-point pipelined FFT-IFFT processor; low-complexity complex multiplier; power consumption; Computer architecture; Digital signal processing; Hardware; Logic gates; OFDM; Pipelines; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ICCE), 2011 IEEE International Conference on
Conference_Location
Las Vegas, NV
ISSN
2158-3994
Print_ISBN
978-1-4244-8711-0
Type
conf
DOI
10.1109/ICCE.2011.5722673
Filename
5722673
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