Multi-access integrated memory management for deeply pipelined processors

Author

Nasibi, O. ; Nourani, M. ; Fakhraie, M. ; Dezfoli, A.G.

Author_Institution

Dept. of Electr. & Comput. Eng., Tehran Univ., Iran

fYear

1999

fDate

22-24 Nov. 1999

Firstpage

285

Lastpage

289

Abstract

In processors with deeply pipelined architecture and numerous buses, management of memory is an important issue. In these processors, each stage of the pipeline might act separately from others, and thus they might have concurrent memory requests. In this paper, we introduce a new method to manage different memory types with multiple sectors in these processors. This method will reduce possible memory conflicts to a minimum and improves performance without using multi-port memory.

Keywords

digital signal processing chips; integrated circuit modelling; integrated memory circuits; parallel architectures; pipeline processing; storage management; DSP; buses; concurrent memory requests; deeply pipelined architecture; deeply pipelined processors; memory conflicts; memory management; memory performance; memory types; multi-access integrated memory management; multi-port memory; multiple processor sectors; pipeline stages; Circuits; Communication industry; Digital signal processing; Digital signal processing chips; Instruments; Laboratories; Memory management; Pipelines; Read-write memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 1999. ICM '99. The Eleventh International Conference on

Print_ISBN

0-7803-6643-3

Type

conf

DOI

10.1109/ICM.2000.884860

Filename

884860