Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture

Author

Sheibanyrad, A. ; Panades, I. Miro ; Greiner, A.

Author_Institution

Pierre et Marie Curie Univ., Paris

fYear

2007

fDate

16-20 April 2007

Firstpage

1

Lastpage

6

Abstract

This paper presents a systematic comparison between two different implementations of a distributed network on chip: fully asynchronous and multi-synchronous. The NoC architecture has been designed to be used in a globally asynchronous locally synchronous clusterized multi processors system on chip. The 5 relevant parameters are silicon area, network saturation threshold, communication throughput, packet latency and power consumption. Both architectures have been physically implemented and simulated by SystemC/VHDL co-simulation. The electrical parameters have also been evaluated by post layout SPICE simulation for a 90nm CMOS fabrication process, taking into account the long wire effects

Keywords

CMOS digital integrated circuits; SPICE; hardware description languages; network-on-chip; 90 nm; CMOS fabrication process; SPICE; SystemC/VHDL co-simulation; asynchronous implementation; clusterized multi processors system-on-chip; communication throughput; distributed network-on-chip; globally asynchronous locally synchronous SoC; long wire effect; multisynchronous implementation; network saturation threshold; packet latency; power consumption; silicon area; CMOS process; Delay; Energy consumption; Fabrication; Network-on-a-chip; SPICE; Silicon; System-on-a-chip; Throughput; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07

Conference_Location

Nice

Print_ISBN

978-3-9810801-2-4

Type

conf

DOI

10.1109/DATE.2007.364439

Filename

4211949