I/O pad assignment based on the circuit structure

Author

Pedram, Massoud ; Chaudhary, Kamal ; Kuh, Ernest S.

Author_Institution

Electron. Res. Lab., California Univ., Berkeley, CA, USA

fYear

1991

fDate

14-16 Oct 1991

Firstpage

314

Lastpage

318

Abstract

An algorithm is presented for assigning off-chip I/O pads for a logic circuit. The technique, which is based on the analysis of the circuit structure and path delay constraints, uses linear placement, goal-programming, linear-sum assignment and I/O pad clustering to assign locations to I/O pads. The I/O pad assignment is then used by placement tools. Experimental data show that as a result of using the I/O pad assignment procedure, the total interconnection length and circuit delay (after placement and routing) are reduced by 8-15% and 3-4%, respectively. This technique is general and can handle I/O pad assignment prior to logic synthesis or detailed placement procedures

Keywords

circuit layout CAD; delays; logic CAD; logic circuits; I/O pad assignment; I/O pad clustering; circuit delay; circuit structure; interconnection length; linear placement; linear-sum assignment; logic circuit; path delay constraints; Atherosclerosis; Circuit analysis; Circuit synthesis; Combinational circuits; Design optimization; Equations; Integrated circuit interconnections; Logic circuits; Logic design; Logic programming;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2270-9

Type

conf

DOI

10.1109/ICCD.1991.139906

Filename

139906