Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio

Author

Mohata, D.K. ; Bijesh, R. ; Zhu, Y. ; Hudait, M.K. ; Southwick, R. ; Chbili, Z. ; Gundlach, D. ; Suehle, J. ; Fastenau, J.M. ; Loubychev, D. ; Liu, A.K. ; Mayer, T.S. ; Narayanan, V. ; Datta, S.

Author_Institution

Electr. Eng., Pennsylvania State Univ., University Park, PA, USA

fYear

2012

fDate

12-14 June 2012

Firstpage

53

Lastpage

54

Abstract

Staggered tunnel junction (GaAs_0.35Sb_0.65/In_0.7Ga_0.3As) is used to demonstrate heterojunction tunnel FET (TFET) with the highest drive current, I_on, of 135μA/μm and highest I_on/I_off ratio of 2.7×10⁴ (V_ds=0.5V, V_on-V_off=1.5V). Effective oxide thickness (EOT) scaling (using Al₂O₃/HfO₂ bilayer gate stack) coupled with pulsed I-V measurements (suppressing D_it response) enable demonstration of steeper switching TFET.

Keywords

III-V semiconductors; aluminium compounds; field effect transistors; gallium arsenide; hafnium compounds; interface states; oxidation; tunnel transistors; Al₂O₃-HfO₂; EOT scaling; GaAs_0.35Sb_0.65-In_0.7Ga_0.3As; bilayer gate stack; effective oxide thickness; heteroepitaxy; heterojunction tunnel FET; high drive current; high on-off ratio; interface state; pulsed I-V measurement; scaled gate stack; staggered tunnel junction; switching TFET; voltage 0.5 V; voltage 1.5 V; Gallium arsenide; Heterojunctions; Logic gates; Performance evaluation; Pulse measurements; Switches; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2012 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4673-0846-5

Electronic_ISBN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2012.6242457

Filename

6242457