DocumentCode
2644142
Title
Hybrid memory cube new DRAM architecture increases density and performance
Author
Jeddeloh, Joe ; Keeth, Brent
fYear
2012
fDate
12-14 June 2012
Firstpage
87
Lastpage
88
Abstract
Multi-core processor performance is limited by memory system bandwidth. The Hybrid Memory Cube is a three-dimensional DRAM architecture that improves latency, bandwidth, power and density. Through-silicon vias (TSVs), 3D packaging and advanced CMOS performance enable a new approach to memory system architecture. Heterogeneous die are stacked with significantly more connections, thereby reducing the distance signals travel.
Keywords
CMOS memory circuits; DRAM chips; integrated circuit packaging; logic design; three-dimensional integrated circuits; 3D packaging; TSV; advanced CMOS performance; hybrid memory cube; memory system bandwidth; three dimensional DRAM architecture; through silicon via; Bandwidth; Multicore processing; Random access memory; Through-silicon vias; Timing; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2012 Symposium on
Conference_Location
Honolulu, HI
ISSN
0743-1562
Print_ISBN
978-1-4673-0846-5
Electronic_ISBN
0743-1562
Type
conf
DOI
10.1109/VLSIT.2012.6242474
Filename
6242474
Link To Document