Functional verification of external memory interface IP core based on restricted random testbench

The design of SoC system, random test is becoming an application for IP cores verification gradually. In order to test the integrated EMIF IP core, the restricted random verification method is used with added flexible generation of parameterized script files and adaptable random test points. Based on the verification environment built, some tasks were created and passed as transactions according to the analysis of simulation interface and output results. Standard memory modules were integrated with timing factors to support verification. Comparing with the direct verification, the method present in this paper is much more flexible and practicable, and can improve the whole efficiency of verification.