DocumentCode
2646176
Title
Error bound reduction for fixed-width modified Booth multiplier
Author
Cho, Kyung-Ju ; Lee, Seong-Min ; Park, Seong-Hun ; Chung, Jin-Gyun
Author_Institution
Dept. of Electron. & Inf. Eng., Chonbuk Nat. Univ., Chonju, South Korea
Volume
1
fYear
2004
fDate
7-10 Nov. 2004
Firstpage
508
Abstract
The maximum error has serious effect on the performance of fixed-width multipliers that receive W-bit inputs and produce W-bit products. In this paper, we analyze the error bound of fixed-width modified Booth multiplier. Then, we present a method that can be used to reduce the maximum error. By simulations, it is shown that the performance of the proposed fixed-width multiplier is pretty close to that of the multiplier with rounding scheme.
Keywords
error analysis; multiplying circuits; vector quantisation; W-bit input; W-bit product; error bound reduction; fixed-width modified Booth multiplier; rounding scheme; Encoding; Error analysis; Error compensation; Log periodic antennas; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on
Print_ISBN
0-7803-8622-1
Type
conf
DOI
10.1109/ACSSC.2004.1399184
Filename
1399184
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