Low power design of block FIR filtering for high throughput rate applications

A novel implementation of a low power FIR filtering algorithm is presented. The algorithm is distributed such that an input to a MAC, which is the coefficient of an FIR filter, remains unchanged during four consecutive multiplication and accumulation processes. This reduces switching activity and hence power consumption. For the computation of final result, four partial sums in each MAC units are summed together using local buses between the MACs, which reduces effective capacitance and hence improves speed. A 16-bit floating-point format of TMS320C3x DSP is used. Dada tree multiplier and conditional sum adders played important role to further increase the multiplication speed and reduction in power consumption.