Congestion-driven floorplanning based on two-stage optimization

In current VLSI design, routing congestion becomes a critical issue with deep submicron design technology. In order to avoid the rip-up and reroute which is a time-consuming process after the placement stage, in this paper, we proposed a new two-stage floorplanning approach for congestion optimization. In our approach we use the method of probability-estimation which uses the extended bounding box to evaluate the routing of nets. We also take use of the strategy of cell perturb to eliminate the routing congestion. Further reduction in congestion is obtained by our algorithm which guided by congestion. We have tested our approach on the MCNC benchmark circuits. The experiments show that our algorithms is efficient, stable and can reduce congestion largely. Compared with the traditional congestion-driven floorplanning, our 2-stage approach can alleviate the congestion efficiently in much shorter time.