DocumentCode
2648779
Title
Parallel processing architectures for rank order and stack filters
Author
Lucke, Lori E. ; Parhi, Keshab K.
Author_Institution
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear
1993
fDate
25-27 Oct 1993
Firstpage
65
Lastpage
76
Abstract
To achieve additional speedup in rank order and stack filter architectures requires the use of parallel processing techniques such as pipelining and block processing. Pipelining is well understood but few block architectures have been developed for rank order and stack filtering. Block processing is essential when the architecture reaches the throughput limits caused by the underlying technology. A trivial block structure repeats a single input, single output structure to generate a multiple input, multiple output structure and can achieve speedups equal to the block size (or the number of multiple outputs). Unlike linear filters, the rank order and stack filter outputs are calculated using comparisons. It is possible to share these comparisons within the block structure. The authors introduce a systematic method for applying block processing to the rank order and stack filters. This method takes advantage of shared comparisons within the block structure to generate a block filter with shared substructures whose complexity is reduced. Furthermore, block processing is important for the generation of low power designs. Trivial block structures generate low power designs up to a certain limit. The authors demonstrate how block structures with shared substructures are used to generate designs with arbitrarily low power
Keywords
digital filters; nonlinear filters; parallel architectures; pipeline processing; block architectures; block processing; block size; low power designs; pipelining; rank order filters; shared substructures; stack filters; techniques; throughput limits; Corporate acquisitions; Filtering; Merging; Nonlinear filters; Parallel processing; Pipeline processing; Power generation; Sorting; Throughput; Windows;
fLanguage
English
Publisher
ieee
Conference_Titel
Application-Specific Array Processors, 1993. Proceedings., International Conference on
Conference_Location
Venice
ISSN
1063-6862
Print_ISBN
0-8186-3492-8
Type
conf
DOI
10.1109/ASAP.1993.397121
Filename
397121
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