DocumentCode
2649412
Title
Power aware design for next generation´s Many Cores computing platforms
Author
Zafalon, Roberto
Author_Institution
STMicroelectronics, Eur. R&D & Public Affairs., Agrate Brianza, Italy
fYear
2009
fDate
20-23 Oct. 2009
Firstpage
777
Lastpage
779
Abstract
We describe a comprehensive set of design techniques, applicable at different levels of abstraction that have proven to bring great potential for power optimization in industrial embedded multi-processing platforms.
Keywords
embedded systems; low-power electronics; multiprocessing systems; industrial embedded multiprocessing platform; next generation many cores computing; power aware design; power optimization; Computer aided manufacturing; Computer architecture; Computer networks; Design optimization; Embedded computing; Energy consumption; High performance computing; Mobile computing; Multimedia computing; Network-on-a-chip; Multi Processing architecture; Network on Chip; Ultra low power computing platform; leakage power; low power design; power optimization; system-level energy optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location
Changsha, Hunan
Print_ISBN
978-1-4244-3868-6
Electronic_ISBN
978-1-4244-3870-9
Type
conf
DOI
10.1109/ASICON.2009.5351281
Filename
5351281
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